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STTS424E02
Memory module temperature sensor with a 2 Kb SPD EEPROM
Features
STTS424E02 includes a JEDEC JC 42.4 compatible temperature sensor, integrated with industry standard 2 Kbit Serial Presence Detect (SPD) EEPROM
Temperature sensor

TDFN8 (DN)(a) 2 mm x 3 mm (max height 0.80 mm)
Temperature sensor resolution: 0.25C (typ)/LSB Temperature sensor accuracy: - 1C from +75C to +95C - 2C from +40C to +125C - 3C from -40C to +125C ADC conversion time: 125 ms (max) Supply voltage: 2.7 V to 3.6 V Maximum operating supply current: 210 A (EEPROM inactive) Hysteresis selectable set points from: 0, 1.5, 3, 6.0C Ambient temperature sensing range: -40C to +125C
DFN8 (DA) 2 mm x 3 mm (max height 0.90 mm)

Two-wire bus

2-wire SMBus/I2C - compatible serial interface Temperature sensor supports SMBus timeout Supports up to 400 kHz transfer rate
Packages

2Kb SPD EEPROM

Functionality identical to ST's M34E02 SPD EEPROM Permanent and reversible software data protection for the lower 128 bytes Single supply voltage: 2.7 V to 3.6 V Byte and page write (up to 16 bytes) Self-time WRITE cycle (5 ms, max) Automatic address incrementing More than 1 million erase/WRITE cycles Operating temperature range: - -40C to +85C (DA package only) - -40C to +125C (DN package only)
DN: 2 mm x 3 mm TDFN8, height: 0.80 mm (max)(a) DA: 2 mm x 3 mm DFN8, height: 0.90 mm (max) RoHS compliant, halogen-free
a. Compliant to JEDEC MO-229, WCED-3
June 2008
Rev 6
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www.st.com 1
Contents
STTS424E02
Contents
1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Serial communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 Device type identifier (DTI) code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 A0, A1, A2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS (ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SDA (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SCL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 EVENT (open drain) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD (power) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Temperature sensor operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1 3.2 3.3 SMBus/I2C communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 SMBus/I2C slave sub-address decoding . . . . . . . . . . . . . . . . . . . . . . . . . 13 SMBus/I2C AC timing consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
Temperature sensor registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Capability register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.1 4.1.2 Alarm window trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Critical trip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2
Configuration register (read/write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 Event thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Event output pin functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.3 4.4 4.5 4.6
Temperature register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1 Temperature format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Temperature trip point registers (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Manufacturer ID register (read-only) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device ID and device revision ID register (read-only) . . . . . . . . . . . . . . . 27
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STTS424E02
Contents
5
SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.1 5.2 5.3 5.4 2 Kb SPD EEPROM operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Internal device reset - SPD EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Setting the write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.4.1 5.4.2 SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5
Write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5.1 5.5.2 5.5.3 Byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Minimizing system delays by polling on ACK . . . . . . . . . . . . . . . . . . . . . 33
5.6
Read operations - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6.1 5.6.2 5.6.3 5.6.4 Random address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Current address read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Sequential read - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Acknowledge in read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
6 7
Initial delivery state - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Use in a memory module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1 Programming the SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
7.1.1 7.1.2 DIMM isolated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 DIMM inserted in the application motherboard . . . . . . . . . . . . . . . . . . . 37
8 9 10 11 12 13 14
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Package marking information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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List of tables
STTS424E02
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AC SMBus and I2C compatibility timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Temperature sensor registers summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pointer register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Pointer register select bits (type, width, and default values). . . . . . . . . . . . . . . . . . . . . . . . 17 Capability register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Capability register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Configuration register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Configuration register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Hysteresis as applied to temperature movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Legend for Figure 9: Event output boundary timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Temperature register bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Temperature trip point register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Alarm temperature upper boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Alarm temperature lower boundary register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Critical temperature register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Manufacturer ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device ID and device revision ID register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device select code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 DRAM DIMM connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Acknowledge when writing data or defining the write-protection (instructions with R/W bit=0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Acknowledge when reading the write protection (instructions with R/W bit=1). . . . . . . . . . 38 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 DC/AC characteristics - temperature sensor component with EEPROM . . . . . . . . . . . . . . 40 DFN8 - 8-lead dual flat, no-lead (2 mm x 3 mm) mechanical data (DA) . . . . . . . . . . . . . . 43 TDFN8 - 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN) . . . . . . . . . . 45 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Parameters for landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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STTS424E02
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 DFN8 and TDFN8 connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SMBus/I2C write to pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 SMBus/I2C write to pointer register, followed by a read data word. . . . . . . . . . . . . . . . . . . 12 SMBus/I2C write to pointer register, followed by a write data word . . . . . . . . . . . . . . . . . . 13 SMBus/I2C timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Event output boundary timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Result of setting the write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Setting the write protection (WC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write mode sequences in a non write-protected area of SPD . . . . . . . . . . . . . . . . . . . . . . 32 Write cycle polling flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Read mode sequences - SPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DFN8 - 8-lead dual flat, no-lead (2 mm x 3 mm) package outline (DA) . . . . . . . . . . . . . . . 42 TDFN8 - 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN) . . . . . . . . . . 44 DA package topside marking information (DFN-8L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DN package topside marking information (TDFN-8L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Landing pattern - TDFN package (DN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Description
STTS424E02
1
Description
The STTS424E02 is targeted for DIMM Modules in Mobile Personal Computing Platforms (Laptops), Server Memory Modules and other industrial applications. The Thermal Sensor (TS) in the STTS424E02 is compliant with the JEDEC specification, which defines Memory Module Thermal Sensors requirements for Mobile platforms. The 2 Kbit Serial Presence Detect (SPD) I2C-compatible Electrically Erasable Programmable Memory (EEPROM) in the STTS424E02 is organized as 256 x8 bits and is functionally identical to the industry standard M34E02. The TS-SPD EEPROM combination provides space as well as cost savings for Mobile and Server Platform Dual Inline Memory Modules (DIMM) manufacturers, as it is packaged in the compact 2 mm x 3 mm 8-lead DFN package which is available in two variations. The DA package has a maximum height of 0.90 mm. The DN package has an identical footprint as the DA package with a thinner maximum height of 0.80 mm. The DN package is compliant to JEDEC MO-229, variation WCED-3. The temperature sensor includes a band gap-based temperature sensor and 10-bit Analogto-Digital Converter (ADC) which monitor and digitize the temperature to a resolution of up to 0.25C. The typical accuracies over these temperature ranges are:

3C (max) over the full temperature measurement range of -40C to 125C, 2C in the +40C to +125C temperature range, and 1C in the +75C to +95C temperature range.
The temperature sensor in the STTS424E02 is specified for operating at supply voltages from 2.7 V to 3.6 V. Operating at 3.3 V, the supply current is 100 A (typ). The on-board sigma delta ADC converts the measured temperature to a digital value that is calibrated in C. For Fahrenheit applications, a lookup table or conversion routine is required. The STTS424E02 is factory-calibrated and requires no external components to measure temperature. The digital temperature sensor component has user-programmable registers that provide the capabilities for DIMM temperature-sensing applications. The open drain Event output pin is active when the monitoring temperature exceeds a programmable limit, or it falls above or below an alarm window. The user has the option to set the Event output as a critical temperature output. This pin can be configured to operate in either a comparator mode for thermostat operation or in interrupt mode. The 2 Kbit serial EEPROM memory in the STTS424E02 has the ability to permanently lock the data in its first half (upper) 128 bytes (locations 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs with SPD. All of the information concerning the DRAM module configuration (e.g. access speed, size, and organization) can be kept write protected in the first half of the memory. The second half (lower) 128 bytes of the memory can be write protected using two different software write protection mechanisms. By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resettable. In the STTS424E02 the EEPROM Write Control (WC) is always held low. Thus, the write protection of the memory array is dependent on whether the software protection has been set.
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STTS424E02
Serial communications
2
Serial communications
The STTS424E02 has a simple 2-wire SMBusTM/I2C-compatible digital serial interface which allows the user to access both the 2 Kbit serial EEPROM and the data in the temperature register at any time. It communicates via the serial interface with a master controller which operates at speeds of up to 400 kHz. It also gives the user easy access to all of the STTS424E02 registers in order to customize device operation.
2.1
Device type identifier (DTI) code
The JEDEC temperature sensor and EEPROM each have their own unique I2C address, which ensures that there are no compatibility or data translation issues. This is due to the fact that each of the devices have their own 4-bit DTI code, while the remaining three bits are configurable. This enables the EEPROM and thermal sensors to provide their own individual data via their unique addresses and still not interfere with each others' operation in any way. The DTI codes are:

'0011' for the TS, and '1010' for addressing the EEPROM memory array, and `0110' to access the software write protection settings of the EEPROM.
Note:
The EEPROM in the STTS424E02 package has its WC pin internally tied to the VSS (Ground) pad inside the package while the A0, A1, and A2 pins in the logic diagram (see Figure 1 on page 8) correspond to the chip enable pins E0, E1 and E2 of EEPROM.
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Serial communications Figure 1. Logic diagram
VDD SDA(1) SCL A2 A1 A0 STTS424E02 EVENT(1)
STTS424E02
VSS
AI12261
1. SDA and EVENT are open drain.
Table 1.
Pin 1 2 3 4 5 6 7 8
Signal names
Symbol A0 A1 A2 VSS SDA
(1)
Description Serial bus address selection pin. Can be tied to VSS or VDD. Serial bus address selection pin. Can be tied to VSS or VDD. Serial bus address selection pin. Can be tied to VSS or VDD. Supply ground. Serial data. Serial clock. Event output pin. Open drain and active-low. Supply power (2.7 V to 3.6 V).
Direction Input Input Input
Input/output Input Output
SCL EVENT(1) VDD
1. SDA and EVENT are open drain.
Note:
See Section 2.2: Pin descriptions on page 10 for details. Figure 2. DFN8 and TDFN8 connections (top view)
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VDD EVENT(1) SCL SDA(1)
AI12262
1. SDA and EVENT are open drain.
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STTS424E02 Figure 3. Block diagram
8 VDD
Serial communications
Temperature Sensor Logic Control Comparator Timing ADC EVENT 7
Capability Register Configuration Register Temperature Register
Upper Register Lower Register Critical Register Manufacturer ID Device ID/ Revision
2Kb SPD EEPROM Software Write Protect WC VSS 1 2 3 A0 A1 A2 E0 E1 E2
Address Pointer Register
SCL 6 SMBus/I2C Interface SDA 5
VSS 4
AI12278a
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Serial communications
STTS424E02
2.2
2.2.1
Pin descriptions
A0, A1, A2
A2, A1, and A0 are selectable address pins for the 3 LSBs of the I2C interface address. They can be set to VDD or GND to provide 8 unique address selections. These pins are internally connected to the E2, E1, E0 (chip selects) of EEPROM.
2.2.2
VSS (ground)
This is the reference for the power supply. It must be connected to system ground.
2.2.3
SDA (open drain)
This is the Serial Data input/output pin.
2.2.4
SCL
This is the Serial Clock input pin.
2.2.5
EVENT (open drain)
This output pin is open drain and active-low, and functions as an Alert interrupt.
2.2.6
VDD (power)
This is the supply voltage pin, and ranges from +2.7 V to +3.6 V.
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STTS424E02
Temperature sensor operation
3
Temperature sensor operation
The temperature sensor continuously monitors the ambient temperature and updates the temperature data register at least eight times per second. Temperature data is latched internally by the device and may be read by software from the bus host at any time. The SMBus/I2C slave address selection pins allow up to 8 such devices to co-exist on the same bus. This means that up to 8 memory modules can be supported, given that each module has one such slave device address slot. After initial power-on, the configuration registers are set to the default values. The software can write to the configuration register to set bits per the bit definitions in Section 3.1: SMBus/I2C communications. For details of operation and usage of 2 Kb SPD EEPROM, refer to Section 5: SPD EEPROM operation.
3.1
SMBus/I2C communications
The registers in this device are selected by the Pointer register. At power-up, the Pointer register is set to "00", which is the Capability register location. The Pointer register latches the last location it was set to. Each data register falls into one of three types of user accessibility: 1. 2. 3. Read-only Write-only, and WRITE/READ same address
A WRITE to this device will always include the address byte and the pointer byte. A WRITE to any register other than the pointer register, requires two data bytes. Reading this device is achieved in one of two ways:
If the location latched in the Pointer register is correct (most of the time it is expected that the Pointer register will point to one of the Read Temperature registers because that will be the data most frequently read), then the READ can simply consist of an address byte, followed by retrieval of the two data bytes. If the Pointer register needs to be set, then an address byte, pointer byte, repeat start, and another address byte will accomplish a READ.
The data byte transfers the MSB first. At the end of a READ, this device can accept either an Acknowledge (ACK) or No Acknowledge (No ACK) status from the Master. The No ACK status is typically used as a signal for the slave that the Master has read its last byte. This device subsequently takes up to 125 ms to measure the temperature.
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Temperature sensor operation Figure 4. SMBus/I2C write to pointer register
SCL
1 9 1 9
STTS424E02
SDA
0 0 1 1 A2 A1 A0 R/W 0 0 0 0 0 D2 D1 D0
Start by Master
Address Byte ACK by STTS424E02
Pointer Byte ACK by STTS424E02
AI12264
Figure 5.
SMBus/I2C write to pointer register, followed by a read data word
SCL
1 9 1 9
SDA
0 0 1 1 A2 A1 A0 R/W 0 0 0 0 0 D2 D1 D0
Start by Master
Address Byte ACK by STTS2002
Pointer Byte ACK by STTS2002
SCL (continued) SDA (continued) Repeat Start by Master
1
9
1
9
1
9
0
0
1
1
A2 A1 A0 R/W
D15
D14
D13
D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Address Byte ACK by STTS2002
MSB Data Byte ACK by Master
LSB Data Byte
Stop Cond. No ACK by by Master Master
AI12265
12/51
STTS424E02 Figure 6.
Temperature sensor operation SMBus/I2C write to pointer register, followed by a write data word
SCL
1 9 1 9
SDA
0 0 1 1 A2 A1 A0 R/W 0 0 0 0 0 D2 D1 D0
Start by Master
Address Byte ACK by STTS424E02
Pointer Byte ACK by STTS424E02
SCL (continued)
1
9
1
9
SDA (continued)
D15
D14
D13
D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MSB Data Byte ACK by STTS424E02
LSB Data Byte
Stop Cond. No ACK by by Master STTS424E02
AI14012
3.2
SMBus/I2C slave sub-address decoding
The physical address for the TS is different than that used by the EEPROM. The TS physical address is binary 0 0 1 1 A2 A1 A0 RW, where A2, A1, and A0 are the three slave subaddress pins, and the LSB "RW" is the READ/WRITE flag. The EEPROM physical address is binary 1 0 1 0 A2 A1 A0 RW for the memory array and is 0 1 1 0 A2 A1 A0 RW for permanently set write protection mode.
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Temperature sensor operation
STTS424E02
3.3
SMBus/I2C AC timing consideration
In order for this device to be both SMBus- and I2C-compatible, it complies to a subset of each specification. The requirements which enable this device to co-exist with devices on either an SMBus or an I2C bus include:

The SMBus minimum clock frequency is required. The 300 ns SMBus data hold time (THD:DAT) is required (see Figure 7 and Table 2 on page 15. The SMBus time-out is maximum 40 ms (temperature sensor only).
Note:
Since the voltage levels are specified only within 3.3 V 10%, there are no compatibility concerns with the SMBus/I2C DC specifications. Figure 7. SMBus/I2C timing diagram
tR tLOW tF SCL VIH VIL tHD:STA tBUF tHD:DAT SDA VIH VIL P S S P
A12266
tSU:STA tHIGH tSU:DAT tSU:STO
14/51
STTS424E02 Table 2.
Symbol tBUF tHD:STA tSU:STA(1) tHIGH tLOW tF tR tSU:DAT tHD:DAT tSU:STO tW
(2)
Temperature sensor operation
AC SMBus and I2C compatibility timings
DA package Parameter Min Bus free time between stop (P) and start (S) conditions Hold time after (repeated) start condition. After this period, the first clock cycle is generated. Repeated start condition setup time Clock high period Clock low period Clock/data fall time Clock/data rise time Data setup time Data hold time Stop condition setup time WRITE time for EEPROM SMBUS/I2C clock frequency Bus timeout (temperature sensor only) 4.7 4.0 4.7 4.0 4.7 - - 250 300 4.0 - 10 25 Max - - - - - 300 1000 - - - 10 100 50 Min 1.3 0.6 1.3 0.6 1.3 - - 100 300 0.6 - 10 25 Max - - - - - 300 300 - - - 10 400 50 s s s s s ns ns ns ns s ms KHz ms DN package Units
fSCL ttimeout
1. For a restart condition, or following a WRITE cycle. 2. This parameter reflects maximum WRITE time for EEPROM.
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Temperature sensor registers
STTS424E02
4
Temperature sensor registers
The temperature sensor component is comprised of various user-programmable registers. These registers are required to write their corresponding addresses to the Pointer register. They can be accessed by writing to their respective addresses (see Table 3). Pointer register Bits 7-3 must always be written to '0' (see Table 4). This must be maintained, as not setting these bits to '0' may keep the device from performing to specifications. The main registers include:

Capability register (read-only) Configuration register (read/write) Temperature register (read-only) Temperature trip point registers (r/w), including - - - Alarm Temperature Upper Boundary, Alarm Temperature Lower Boundary, and Critical Temperature.

Manufacturer ID register format Device ID and device revision ID register format
See Table 5 on page 17 for Pointer register selection bit details. Table 3. Temperature sensor registers summary
Register name Address pointer C-grade 00 01 02 03 04 05 06 07 Capability B-grade Configuration Alarm temperature upper boundary trip Alarm temperature lower boundary trip Critical temperature trip Temperature Manufacturer's ID DA package Device ID/revision DN package 0x0001 0x002F 0x0000 0x0000 0x0000 0x0000 Undefined 0x104A 0x0000 Power-on default Undefined 0x002D
Address (Hex) Not applicable
Table 4.
MSB Bit7 0
Pointer register format
LSB Bit6 0 Bit5 0 Bit4 0 Bit3 0 Bit2 P2 Bit1 P1 Bit0 P0
Pointer/register select bits
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STTS424E02 Table 5.
P2 P1
Temperature sensor registers
Pointer register select bits (type, width, and default values)
P0 Name Register description C-grade Width Type (bits) (R/W) 16 B-grade 16 16 16 16 16 16 DA package 16 DN package R 0x002F R/W R/W R/W R/W R R R 0x0001 0x0000 0x0000 0x0000 0x0000 0x0000 0x104A 0x0000 Default state (POR) 0x002D
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
CAPA CONF UPPER LOWER
Thermal sensor capabilities Configuration Alarm temperature upper boundary Alarm temperature lower boundary
CRITICAL Critical temperature TEMP MANU ID Temperature Manufacturer ID Device ID/revision
4.1
Capability register (read-only)
This 16-bit register is Read-only, and provides the TS capabilities which comply with the minimum JEDEC 424.4 specifications (see Table 6 and Table 7 on page 18). The STTS424E02 provides temperatures at 0.25 resolution (10-bit).
4.1.1
Alarm window trip
The device provides a comparison window with an upper temperature trip point in the Alarm Upper Boundary register, and a lower trip point in the Alarm Lower Boundary register. When enabled, the Event output will be triggered whenever entering or exiting (crossing above or below) the Alarm window.
4.1.2
Critical trip
The device can be programmed in such a way that the Event output is only triggered when the temperature exceeds the critical trip point. The Critical Temperature setting is programmed in the Critical Temperature register. When the temperature sensor reaches the critical temperature value in this register, the device is automatically placed in Comparator mode, which means that the Critical Event output cannot be cleared by using software to set the Clear Event bit.
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Temperature sensor registers Table 6.
Bit15 RFU
STTS424E02
Capability register format
Bit14 RFU Bit13 RFU Bit12 RFU Bit11 RFU Bit10 RFU Bit9 RFU Bit8 RFU
Bit7 RFU
Bit6 RFU
Bit5 VHV
Bit4 TRES1
Bit3 TRES0
Bit2 Wider range
Bit1 Higher precision
Bit0 Alarm and critical trips
Table 7.
Bit
Capability register bit definitions
Definition
0
Basic capability - 0 = Alarm and critical trips turned OFF. - 1 = Alarm and critical trips turned ON. Accuracy - 0 = Accuracy 2C over the active range and 3C over the monitoring range (C-Grade). - 1 = High accuracy 1C over the active range and 2C over the monitoring range (B-Grade). Range width - 0 = Values lower than 0C will be clamped and represented as binary value '0'. - 1 = Temperatures below 0C can be read and the Sign bit will be set accordingly. Temperature resolution - 01 = This 10-bit value is fixed for STTS424E02, providing temperatures at 0.25C resolution (LSB). (VHV) High voltage support for A0 (pin 1) - 1 = STTS424E02 supports a voltage up to 10 volts on the A0 pin - (default) Reserved These values must be set to '0'.
1
2
4:3
5 15:6
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STTS424E02
Temperature sensor registers
4.2
Configuration register (read/write)
The 16-bit Configuration register stores various configuration modes that are used to set up the sensor registers and configure according to application and JEDEC requirements (see Table 8 on page 19 and Table 9 on page 20).
4.2.1
Event thresholds
All Event thresholds use hysteresis as programmed in register address 0x01 (Bits 10 through 9) to be set when they de-assert.
4.2.2
Interrupt mode
The Interrupt mode allows an event to occur where software may write a '1' to the Clear Event bit (Bit 5) to de-assert the Event Interrupt output until the next trigger condition occurs.
4.2.3
Comparator mode
Comparator mode enables the device to be used as a thermostat. READs and WRITEs on the device registers will not affect the Event output in Comparator mode. The Event signal will remain asserted until temperature drops outside the range or is re-programmed to make the current temperature "out of range".
4.2.4
Shutdown mode
The STTS424E02 features a Shutdown mode which disables all power-consuming activities (e.g. temperature sampling operations), and leaves the serial interface active. This is selected by setting Shutdown bit (Bit 8) to '1'. In this mode, the devices consume the minimum current (ISHDN), as shown in Table 27 on page 40.
Note:
Bit 8 cannot be set to '1' while Bits 6 and 7 (the lock bits) are set to '1'. The device may be enabled for continuous operation by clearing Bit 8 to '0'. In Shutdown mode, all registers may be read or written to. Power recycling will also clear this bit and return the device to continuous mode as well. Table 8.
Bit15 RFU
Configuration register format
Bit14 RFU Bit13 RFU Bit12 RFU Bit11 RFU Bit10 Bit9 Bit8 Shutdown mode
Hysteresis Hysteresis
Bit7 Critical lock bit
Bit6 Alarm lock bit
Bit5 Clear event
Bit4
Bit3
Bit2
Bit1 Event polarity
Bit0 Event mode
Event output Event output Critical status control event only
19/51
Temperature sensor registers Table 9.
Bit
STTS424E02
Configuration register bit definitions
Definition
0
Event mode - 0 = Comparator output mode (this is the default). - 1 = Interrupt mode; when either of the lock bits is set, this bit cannot be altered until it is unlocked. Event polarity - 0 = Active-low (this is the default). - 1 = Active-high; when either of the lock bits is set, this bit cannot be altered until it is unlocked. Critical Event only - 0 = Event output on alarm or critical temperature event (this is the default). - 1 = Event only if the temperature is above the value in the critical temperature register; when the alarm window lock bit is set, this bit cannot be altered until it is unlocked. Event output control - 0 = Event output disabled (this is the default). - 1 = Event output enabled; when either of the lock bits is set, this bit cannot be altered until it is unlocked. Event status (read-only)(1) - 0 = Event output condition is not being asserted by this device. - 1 = Event output condition is being asserted by this device via the alarm window or critical trip event. Clear Event (write-only)(2) - 0 = No effect. - 1 = Clears the active event in interrupt mode. Alarm window lock bit - 0 = Alarm trips are not locked and can be altered (this is the default). - 1 = Alarm trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with a single WRITE, and do not require double WRITEs. Critical trip lock bit - 0 = Critical trip is not locked and can be altered (this is the default). - 1 = Critical trip register settings cannot be altered. This bit is initially cleared. When set, this bit returns a logic '1' and remains locked until cleared by an internal power-on reset. These bits can be written to with a single WRITE, and do not require double WRITEs. Shutdown mode - 0 = TS is enabled (this is the default). - 1 = Shutdown TS when the shutdown, device, and A/D converter are disabled in order to save power. No event conditions will be asserted; when either of the lock bits is set, this bit cannot be altered until it is unlocked. However, it can be cleared at any time. Hysteresis enable (see Figure 8 and Table 10) - 00 = Hysteresis is disabled. - 01 = Hysteresis is enabled at 1.5C. - 10 = Hysteresis is enabled at 3C. - 11 = Hysteresis is enabled at 6C.
1
2
3
4
5
6
7
8
10:9
1. The actual incident causing the event can be determined from the read temperature register. Interrupt events can be cleared by writing to the clear event bit (writing to this bit will have no effect on overall device functioning). 2. Writing to this register has no effect on overall device functioning in comparator mode. When read, this bit will always return a logic '0' result.
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STTS424E02 Figure 8. Hysteresis
TH
Temperature sensor registers
TH - HYS
TL
TL - HYS
Below Window bit
Above Window bit
AI12270
1. TU = Value stored in the alarm temperature upper boundary trip register. 2. TL = Value stored in the alarm temperature lower boundary trip register. 3. HYS = Absolute value of selected hysteresis
Table 10.
Hysteresis as applied to temperature movement
Below alarm window bit Temperature slope Temperature threshold TL - HYS TL Above alarm window bit Temperature slope Rising Falling Temperature threshold TH TH - HYS
Sets Clears
Falling Rising
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Temperature sensor registers
STTS424E02
4.2.5
Event output pin functionality
The Event outputs can be programmed to be configured as either a comparator output or as an interrupt. This is done by enabling the Output Control bit (Bit 3) and setting the Event mode bit (Bit 0). The output pin polarity can also be specified as active-high or active-low by setting the Event polarity bit (Bit 1). When the Hysteresis bits (Bits 10 and 9) are enabled, hysteresis may be used to sense temperature movement around trigger points. For example, when using the "Above Alarm window" bit (Temperature register Bit 14, see Table 12 on page 24) and hysteresis is set to 3C, as the temperature rises, Bit 14 is set (Bit 14 = 1). The temperature is above the alarm window and the Temperature register contains a value that is greater than the value set in the Alarm Temperature Upper Boundary register (see Table 15 on page 25). If the temperature decreases, Bit 14 will remain set until the measured temperature is less than or equal to the value in the Alarm Temperature Upper Boundary register minus 3C (see Figure 8 on page 21 and Table 10 on page 21 for details. Similarly, when using the "Below Alarm window" bit (Temperature register Bit 13, see Table 12 on page 24) will be set to '0'. The temperature is equal to or greater than the value set in the Alarm Temperature Lower Boundary register (see Table 16 on page 26). As the temperature decreases, Bit 13 will be set to '1' when the value in the Temperature register is less than the value in the Alarm Temperature Lower Boundary register minus 3C (see Figure 8 on page 21 and Table 10 on page 21 for details. The device will retain the previous state when entering the Shutdown mode. If the device enters the Shutdown mode while the EVENT pin is low, the Shutdown current will increase due to the additional event output pull-down current.
Note:
Hysteresis is also applied to the EVENT pin functionality. When either of the Lock bits (Bits 6 and 7) are set, these bits cannot be altered.
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STTS424E02 Figure 9. Event output boundary timings
Temperature sensor registers
TCRIT - THYS TCRIT TUPPER TA TLOWER - THYS TLOWER TLOWER - THYS TUPPER - THYS TUPPER - THYS
Event Output (active-low)
Comparator
Interrupt
S/W Int. Clear
Critical
1
2
13
4
35 7 6 4
2
AI12271
Table 11.
Note 1 2 3 4 5 6 7
Legend for Figure 9: Event output boundary timings.
Event output Event output boundary conditions Comparator Interrupt Critical TA TLOWER TA < TLOWER - THYS TA > TUPPER TA < TUPPER - THYS TA TCRIT TA < TCRIT - THYS H L L H L L L L L L L H H H H H L H 15 0 0 0 0 1 0 14 0 0 1 0 1 1 13 0 1 0 0 0 0 TA bits
When TA TCRIT and TA < TCRIT - THYS, the event output is in comparator mode and bit 0 of the configuration register (interrupt mode) is ignored.
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Temperature sensor registers
STTS424E02
4.3
Temperature register (read-only)
This 16-bit, Read-only register stores the temperature measured by the internal band gap TS as shown inTable 12. The STTS424E02 meets the JEDEC mandatory 0.25C resolution requirement. When reading this register, the MSBs (Bit 15 to Bit 8) are read first, and then the LSBs (Bit 7 to Bit 0) are read. The result is the current-sensed temperature. The data format is 2s complement with one LSB = 0.25C. The MSB has a 128C resolution. The Trip status bits represent the internal temperature trip detection, and are not affected by the status of the Event or Configuration bits (e.g. Event output control or Clear Event). If neither of the Above or Below values are set (i.e. both are 0), then the Temperature is exactly within the user-defined alarm window boundaries.
4.3.1
Temperature format
The 16-bit value used in the Trip Point Set and Temperature Read-back registers is 2s complement, with the LSB equal to 0.0625C (see Table 13). For example: 1. 2. 3. a value of 019Ch represents 25.75C, a value of 07C0h represents 124C, and a value of 1E74h represents -24.75C
All unused resolution bits are set to zero. The MSB will have a resolution of 128C. The STTS424E02 supports the 0.25C/LSB only. The upper 3 bits indicate Trip status based on the current temperature, and are not affected by the Event output status. Table 12. Temperature register format
Sign MSB Bit 15 Above critical input(1) Bit 14 Bit 13 Bit 12 Bit Bit Bit Bit Bit Bit Bit Bit Bit 11 10 9 8 7 6 5 4 3 Temperature LSB Bit 2 Bit 1 0 Bit 0 0
Above Below alarm alarm window(1) window(1)
1. See Table 13 for explanation.
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STTS424E02 Table 13.
Bit
Temperature sensor registers Temperature register bit definitions
Definition with Hysteresis = 0 Below (temperature) alarm window - 0 = Temperature is equal to or above the alarm window lower boundary temperature. - 1 = Temperature is below the alarm window. Above (temperature) alarm window. - 0 = Temperature is equal to or below the alarm window upper boundary temperature. - 1 = Temperature is below the alarm window. Above critical trip - 0 = Temperature is below the critical temperature setting. - 1 = Temperature is equal to or above the critical temperature setting.
13
14
15
4.4
Temperature trip point registers (r/w)
The STTS424E02 Alarm mode registers provide for 11-bit data in 2s compliment format. The data provides for one LSB = 0.25C. All unused bits in these registers are read as '0'. The STTS424E02 has three temperature trip point registers (see Table 14):

Alarm temperature upper boundary threshold (Table 15), Alarm temperature lower boundary threshold (Table 16), and Critical temperature trip point value (Table 17).
Note:
If the upper or lower boundary threshold values are being altered in-system, all interrupts should be turned off until a known state can be obtained to avoid superfluous interrupt activity. Table 14.
P2 0 0 1 P1 1 1 0
Temperature trip point register format
P0 0 1 0 Name UPPER LOWER Register description Alarm temperature upper boundary Alarm temperature lower boundary Width (bits) 16 16 16 Type (R/W) R/W R/W R/W Default state (POR) 00 00 00 00 00 00
CRITICAL Critical temperature
Table 15.
Alarm temperature upper boundary register format
Sign MSB LSB Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 Bit 0 0
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12
Alarm window upper boundary temperature
25/51
Temperature sensor registers Table 16. Alarm temperature lower boundary register format
Sign MSB Bit 15 0 Bit 14 0 Bit 13 0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
STTS424E02
LSB Bit 2 Bit 1 0 Bit 0 0
Alarm window lower boundary temperature
Table 17.
Critical temperature register format
Sign MSB LSB Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 0 Bit 0 0
Bit 15 0
Bit 14 0
Bit 13 0
Bit 12
Critical temperature trip point
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STTS424E02
Temperature sensor registers
4.5
Manufacturer ID register (read-only)
The Manufacturer's ID (Programmed Value 104Ah) in this register is the STMicroelectronics Identification provided by the Peripheral Component Interconnect Special Interest Group (PCiSIG). Table 18.
Bit15 0
Manufacturer ID register format
Bit14 0 Bit13 0 Bit12 1 Bit11 0 Bit10 0 Bit9 0 Bit8 0
Bit7 0
Bit6 1
Bit5 0
Bit4 0
Bit3 1
Bit2 0
Bit1 1
Bit0 0
4.6
Device ID and device revision ID register (read-only)
The Device IDs and Device revision IDs are maintained in this register. The register format is shown in Table 19. The Device IDs and Device revision IDs are currently '0' and will be incremented whenever an update of the device is made. Table 19.
Bit15 0
Device ID and device revision ID register format
Bit14 0 Bit13 0 Bit12 0 Device ID Bit11 0 Bit10 0 Bit9 0 Bit8 0
Bit7 0
Bit6 0
Bit5 0
Bit4 0
Bit3 0
Bit2 0
Bit1 0
Bit0(1) 0 or 1
Device revision ID
1. DA package, bit0 is 0 (see Table 27 on page 40). DN package, bit0 is 1 (see Table 27 on page 40).
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SPD EEPROM operation
STTS424E02
5
5.1
SPD EEPROM operation
2 Kb SPD EEPROM operation
The 2 Kbit serial EEPROM is able to lock permanently the data in its first half (from location 00h to 7Fh). This facility has been designed specifically for use in DRAM DIMMs (Dual in line Memory Modules) with Serial Presence Detect. All the information concerning the DRAM module configuration (such as its access speed, its size, its organization) can be kept write protected in the first half of the memory. The first half of the memory area can be write-protected using two different software write protection mechanisms. By sending the device a specific sequence, the first 128 bytes of the memory become write protected: permanently or resetable. These I2C-compatible electrically erasable programmable memory (EEPROM) devices are organized as 256x8 bits. I2C uses a two wire serial interface, comprising a bi-directional data line and a clock line. The device carries a built-in 4-bit Device Type Identifier code (1010) in accordance with the I2C bus definition to access the memory area and a second Device Type Identifier Code (0110) to define the protection. These codes are used together with the voltage level applied on the three chip enable inputs (A2, A1, A0). These input signals are used to set the value that is to be looked for on the three least significant bits (b3, b2, b1) of the 7-bit Device Select Code. In the end application, A0, A1 and A2 must be directly (not through a pull-up or pull-down resistor) connected to VDD or VSS to establish the Device Select Code. When these inputs are not connected, an internal pull-down circuitry makes (A0,A1,A2) = (0,0,0). The A0 input is used to detect the VHV voltage, when decoding an SWP or CWP instruction (refer to Table 20: Device select code). The device behaves as a slave device in the I2C protocol, with all memory operations synchronized by the serial clock. Read and Write operations are initiated by a START condition, generated by the bus master. The START condition is followed by a Device Select Code and RW bit (as described in Table 20: Device select code), terminated by an acknowledge bit. When writing data to the memory, the memory inserts an acknowledge bit during the 9th bit time, following the bus master's 8-bit transmission. When data is read by the bus master, the bus master acknowledges the receipt of the data byte in the same way. Data transfers are terminated by a STOP condition after an Ack for WRITE, and after a NoAck for READ.
5.2
Internal device reset - SPD EEPROM
In order to prevent inadvertent Write operations during Power-up, a Power On Reset (POR) circuit is included. At Power-up (phase during which VDD is lower than VDDmin but increases continuously), the device will not respond to any instruction until VDD has reached the Power On Reset threshold voltage (this threshold is lower than the minimum VDD operating voltage defined in Table 2: AC SMBus and I2C compatibility timings). Once VDD has passed the POR threshold, the device is reset.
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STTS424E02
SPD EEPROM operation
Prior to selecting the memory and issuing instructions, a valid and stable VDD voltage must be applied. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). At Power-down (phase during which VDD decreases continuously), as soon as VDD drops from the normal operating voltage below the Power On Reset threshold voltage, the device stops responding to any instruction sent to it. Table 20. Device select code
Chip enable signals Memory area select code (two arrays)(2) Set write protection (SWP) Clear write protection (CWP) Permanently set write protection (PSWP)(2) Read SWP Read CWP Read PSWP(2) A2 VSS VSS A2 VSS VSS A2 A1 VSS VDD A1 VSS VDD A1 A0 VHV VHV A0 VHV VHV A0 0 1 1 0 Device type identifier b7(1) 1 b6 0 b5 1 b4 0 Chip enable bits b3 A2 0 0 A2 0 0 A2 b2 A1 0 1 A1 0 1 A1 b1 A0 1 1 A0 1 1 A0 RW b0 RW 0 0 0 1 1 1
1. The most significant bit, b7, is sent first. 2. A0, A1 and A2 are compared against the respective external pins on the memory device.
5.3
Memory addressing
To start communication between the bus master and the slave device, the bus master must initiate a Start condition. Following this, the bus master sends the Device Select Code, shown in Table 20: Device select code (on Serial Data (SDA), most significant bit first). The Device Select Code consists of a 4-bit Device Type Identifier, and a 3-bit Chip Enable "Address" (A2, A1, A0). To address the memory array, the 4-bit Device Type Identifier is 1010b; to access the write-protection settings, it is 0110b. Up to eight memory devices can be connected on a single I2C bus. Each one is given a unique 3-bit code on the Chip Enable (A0, A1, A2) inputs. When the Device Select Code is received, the device only responds if the Chip Enable Address is the same as the value on the Chip Enable (A0, A1, A2) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for Read and 0 for Write operations. If a match occurs on the Device Select code, the corresponding device gives an acknowledgment on Serial Data (SDA) during the 9th bit time. If the device does not match the Device Select code, it deselects itself from the bus, and goes into Standby mode.
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SPD EEPROM operation Table 21. Operating modes
RW bit 1 0 Random address read 1 Sequential read Byte write Page write
1. X = VIH or VIL.
STTS424E02
Mode Current address read
WC(1) X X
Bytes 1 1
Initial sequence START, device select, RW = 1 START, device select, RW = 0, address reSTART, device select, RW = 1
X X VIL VIL 1 1 16
1 0 0
Similar to current or random address read START, device select, RW = 0 START, device select, RW = 0
Figure 10. Result of setting the write protection
FFh Standard Array Memory Area Standard Array 00h Default EEPROM memory area state before write access to the Protect Register 80h 7Fh Standard Array Write Protected Array
FFh
80h 7Fh
00h
State of the EEPROM memory area after write access to the Protect Register
AI01936C
5.4
Setting the write protection
The Write Control (WC) is tied Low, hence the write protection of the memory array is dependent on whether software write-protection has been set. Software write-protection allows the bottom half of the memory area (addresses 00h to 7Fh) to be write protected irrespective of subsequent states of the Write Control (WC) signal. Software write-protection is handled by three instructions:

SWP: Set write protection CWP: Clear write protection PSWP: Permanently set write protection
The level of write-protection (set or cleared) that has been defined using these instructions, remains defined even after a power cycle.
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STTS424E02
SPD EEPROM operation
5.4.1
SWP and CWP
If the software write-protection has been set with the SWP instruction, it can be cleared again with a CWP instruction. The two instructions (SWP and CWP) have the same format as a Byte Write instruction, but with a different Device Type Identifier (as shown in Table 20). Like the Byte Write instruction, it is followed by an address byte and a data byte, but in this case the contents are all "Don't Care" (Figure 11). Another difference is that the voltage, VHV, must be applied on the A0 pin, and specific logical levels must be applied on the other two address pins A1 and A2 (as shown in Table 20).
5.4.2
PSWP
If the software write-protection has been set with the PSWP instruction, the first 128 bytes of the memory are permanently write-protected. This write-protection cannot be cleared by any instruction, or by power-cycling the device, and regardless the state of Write Control (WC). Also, once the PSWP instruction has been successfully executed, the SPD EEPROM no longer acknowledges any instruction (with a Device Type Identifier of 0110) to access the write-protection settings. Figure 11. Setting the write protection (WC = 0)
START
BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY
CONTROL BYTE
WORD ADDRESS
DATA
ACK
ACK
ACK
VALUE VALUE (DON'T CARE) (DON'T CARE)
AI01935B
5.5
Write operations
Following a Start condition the bus master sends a Device Select Code with the RW bit reset to 0. The device acknowledges this, as shown in Figure 12, and waits for an address byte. The device responds to the address byte with an acknowledge bit, and then waits for the data byte. When the bus master generates a Stop condition immediately after the Ack bit (in the "10th bit" time slot), either at the end of a Byte Write or a Page Write, the internal memory Write cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write cycle. During the internal Write cycle, Serial Data (SDA) and Serial Clock (SCL) are ignored, and the device does not respond to any requests.
STOP
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SPD EEPROM operation
STTS424E02
5.5.1
Byte write
After the Device Select Code and the address byte, the bus master sends one data byte. If the addressed location is hardware write-protected, the device replies to the data byte with NoAck, and the location is not modified. If, instead, the addressed location is not Writeprotected, the device replies with Ack. The bus master terminates the transfer by generating a Stop condition, as shown in Figure 12.
5.5.2
Page write
The Page Write mode allows up to 16 bytes to be written in a single Write cycle, provided that they are all located in the same page in the memory: that is, the most significant memory address bits are the same. If more bytes are sent than will fit up to the end of the page, a condition known as `roll-over' occurs. This should be avoided, as data starts to become overwritten in an implementation dependent way. The bus master sends from 1 to 16 bytes of data, each of which is acknowledged by the device if Write Control (WC) is Low. After each byte is transferred, the internal byte address counter (the 4 least significant address bits only) is incremented. The transfer is terminated by the bus master generating a Stop condition. Figure 12. Write mode sequences in a non write-protected area of SPD
ACK BYTE WRITE
START
ACK DATA IN
ACK
DEV SEL R/W
BYTE ADDR
ACK PAGE WRITE
START
ACK DATA IN 1
ACK DATA IN 2
DEV SEL R/W ACK
BYTE ADDR
ACK DATA IN N
STOP
STOP
AI01941
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STTS424E02 Figure 13. Write cycle polling flowchart using ACK
WRITE Cycle in Progress
SPD EEPROM operation
START Condition DEVICE SELECT with RW = 0
NO First byte of instruction with RW = 0 already decoded by the device
ACK Returned YES
NO
Next Operation is Addressing the Memory
YES
ReSTART
Send Address and Receive ACK
STOP
NO
START Condition
YES
DATA for the WRITE Operation
DEVICE SELECT with RW = 1
Continue the WRITE Operation
Continue the Random READ Operation
AI01847C
5.5.3
Minimizing system delays by polling on ACK
During the internal Write cycle, the device disconnects itself from the bus, and writes a copy of the data from its internal latches to the memory cells. The maximum Write time (tw) is shown inTable 2: AC SMBus and I2C compatibility timings , but the typical time is shorter. To make use of this, a polling sequence can be used by the bus master. The sequence, as shown in Figure 13, is:

Initial condition: a Write cycle is in progress. Step 1: the bus master issues a Start condition followed by a Device Select Code (the first byte of the new instruction). Step 2: if the device is busy with the internal Write cycle, no Ack will be returned and the bus master goes back to Step 1. If the device has terminated the internal Write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).
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SPD EEPROM operation
STTS424E02
5.6
Read operations - SPD
Read operations are performed independently of whether hardware or software protection has been set. The device has an internal address counter which is incremented each time a byte is read.
5.6.1
Random address read - SPD
A dummy Write is first performed to load the address into this address counter (as shown in Figure 14) but without sending a Stop condition. Then, the bus master sends another Start condition, and repeats the Device Select Code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a Stop condition.
5.6.2
Current address read - SPD
For the Current Address Read operation, following a Start condition, the bus master only sends a Device Select Code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a Stop condition, as shown in Figure 14, without acknowledging the byte.
5.6.3
Sequential read - SPD
This operation can be used after a Current Address Read or a Random Address Read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 14. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter `rolls-over', and the device continues to output data from memory address 00h.
5.6.4
Acknowledge in read mode
For all Read commands, the device waits, after each byte read, for an acknowledgment during the 9th bit time. If the bus master does not drive Serial Data (SDA) Low during this time, the device terminates the data transfer and switches to its Standby mode.
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STTS424E02 Figure 14. Read mode sequences - SPD
ACK CURRENT ADDRESS READ START DEV SEL R/W NO ACK DATA OUT STOP
SPD EEPROM operation
ACK RANDOM ADDRESS READ START DEV SEL(1) R/W
ACK DEV SEL(1) START
ACK
NO ACK DATA OUT
BYTE ADDR
R/W
ACK SEQUENTIAL CURRENT READ START DEV SEL R/W DATA OUT 1
ACK
ACK
NO ACK
DATA OUT N STOP ACK DEV SEL(1) START R/W ACK DATA OUT 1 ACK
ACK SEQUENTIAL RANDOM READ START DEV SEL(1) R/W
BYTE ADDR
ACK
NO ACK
DATA OUT N STOP
AI01942
1. The seven most significant bits of the device select code of a random read (in the 1st and 3rd bytes) must be identical.
STOP
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Initial delivery state - SPD
STTS424E02
6
Initial delivery state - SPD
The device is delivered with all bits in the memory array set to `1' (each byte contains FFh).
7
Use in a memory module
In the Dual In line Memory Module (DIMM) application, the SPD is soldered directly on to the printed circuit module. The three Chip Enable inputs (A0, A1, A2) must be connected to VSS or VDD directly (that is without using a pull-up or pull-down resistor) through the DIMM socket (see Table 22). The Write Control (WC) of the device is tied to ground to maintain full read and write access. Table 22. DRAM DIMM connections
A2 VSS (0) VSS(0) VSS (0) VSS (0) VDD (1) VDD (1) VDD (1) VDD (1) A1 VSS (0) VSS (0) VDD (1) VDD (1) VSS (0) VSS (0) VDD (1) VDD (1) A0 VSS (0) VDD (1) VSS (0) VDD(1) VSS (0) VDD (1) VSS (0) VDD (1)
DIMM position 0 1 2 3 4 5 6 7
7.1
Programming the SPD
The situations in which the SPD EEPROM is programmed can be considered under two headings:

when the DIMM is isolated (not inserted on the PCB motherboard) when the DIMM is inserted on the PCB motherboard
7.1.1
DIMM isolated
With specific programming equipment, it is possible to define the SPD EEPROM content, using Byte and Page Write instructions, and its write-protection using the SWP and CWP instructions. To issue the SWP and CWP instructions, the DIMM must be inserted in the application-specific slot where the A0 signal can be driven to VHV during the whole instruction. This programming step is mainly intended for use by DIMM makers, whose end application manufacturers will want to clear this write-protection with the CWP on their own specific programming equipment, to modify the lower 128 bytes, and finally to set permanently the write-protection with the PSWP instruction.
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STTS424E02
Use in a memory module
7.1.2
DIMM inserted in the application motherboard
As the final application cannot drive the A0 pin to VHV, the only possible action is to freeze the write-protection with the PSWP instruction. Table 23 and Table 24 show how the Ack bits can be used to identify the write-protection status.
Table 23.
Acknowledge when writing data or defining the write-protection (instructions with R/W bit=0)
WC Input Level Instruction Ack Address Not significant Address Not significant Not significant Not significant Address Not significant Address Ack Data byte Not significant Data Not significant Not significant Not significant Data Not significant Data Ack Write cycle(tW) No No No Yes Yes No Yes Yes
Status
PSWP, SWP or CWP Permanently protected X Page or byte write in lower 128 bytes SWP CWP Protected with SWP 0 PSWP Page or byte write in lower 128 bytes 0 Not Protected Page or byte write PSWP, SWP or CWP
NoAck Ack NoAck Ack Ack Ack Ack Ack
NoAck Ack NoAck Ack Ack Ack Ack Ack
NoAck NoAck NoAck Ack Ack NoAck Ack Ack
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Use in a memory module Table 24.
Status Permanently protected Protected with SWP Not protected
STTS424E02
Acknowledge when reading the write protection (instructions with R/W bit=1)
Instruction PSWP, SWP or CWP SWP CWP PSWP PSWP, SWP or CWP Ack NoAck NoAck Ack Ack Ack Address Not significant Not significant Not significant Not significant Not significant Ack NoAck NoAck NoAck NoAck NoAck Data byte Not significant Not significant Not significant Not significant Not significant Ack NoAck NoAck NoAck NoAck NoAck
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STTS424E02
Maximum ratings
8
Maximum ratings
Stressing the device above the ratings listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 25.
Symbol TSTG TSLD(1) VIO VDD IO PD JA
Absolute maximum ratings
Parameter Storage temperature Lead solder temperature for 10 seconds Input or output voltage - all pins Supply voltage Output current Power dissipation DA package Thermal resistance DN package 130 C/W Value -60 to 150 260 VSS - 0.3 to VDD +0.5 VSS - 0.3 to 6.5 10 320 128 Unit C C V V mA mW C/W
1. Reflow at peak temperature of 255C to 260C for < 30 seconds (total thermal budget not to exceed 180C for between 90 to 150 seconds).
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DC and AC parameters
STTS424E02
9
DC and AC parameters
This section summarizes the operating measurement conditions, and the dc and ac characteristics of the device. The parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 26, Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 26.
Operating and AC measurement conditions
Parameter Conditions 2.7 to 3.6 -40 to 85 5 0.2 to 0.8VDD 0.3 to 0.7VDD Unit V C ns V V
VDD supply voltage - temperature sensor Operating temperature Input rise and fall times Input pulse voltages Input and output timing reference voltages
Table 27.
Sym VDD
DC/AC characteristics - temperature sensor component with EEPROM
Description Supply voltage VDD supply current, active temperature conversions (no communication) VDD supply current, communication only (no conversions) EEPROM (inactive) SCL/SDA = VDD EEPROM (not selected) 100 kHz 400 kHz Test condition(1) Min 2.7 Typ(2) Max 3.3 100 40 115 2.0 1.0 1.0 6 4 VDD falling edge: DA package Power on Reset (POR) threshold VDD falling edge: DN package +75C < TA < +95 2.0 1.0 2.0 3.0 2.0 3.0 4.0 V C C C 0.6 3 5 3.6 210 Unit V A A A mA A A mA A V
IDD
EEPROM, TS shutdown IDD1 Shutdown mode supply current DA package at 85C DN package at 125C
EEPROM inactive, TS shutdown
ISINK
SMBUS output low sink current
SDA forced to 0.6 V
IIH, IIL, Input/output leakage current IOH, IOL
VPOR(3)
Accuracy for corresponding range C-grade 2.7 V VDD 3.6 V
+40C < TA < +125 -40C < TA < +125
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STTS424E02 Table 27.
Sym
DC and AC parameters
DC/AC characteristics - temperature sensor component with EEPROM (continued)
Description Test condition(1) +75C < TA < +95 Min Typ(2) Max 0.5 1.0 2.0 1.0 2.0 3.0 0.25 Resolution 10-bit temperature data 10 Unit C C C C/L SB bits ms mV 0.4 V
Accuracy for corresponding range B-grade 2.7 V VDD 3.6 V
+40C < TA <+ 125 -40C < TA < +125
tCONV THYS VOL1
Conversion time Hysteresis Low level voltage
10-bit Default value EVENT; IOL = 2.1 mA 500
125
SMBus/I2C interface VIH VIL CIN fSCL ttimeout VHV LAO VOL2 ZAIL ZAIH TA Input logic high Input logic low SMBus/I2C input capacitance SMBus/I2C clock frequency SMBus timeout Allowable voltage on pin A0 Leakage on pin A0 Low level voltage SDA (A0, A1, A2) input impedance (A0, A1, A2) input Impedance Ambient operating temperature: DN package -40 125 C In overvoltage state IOL = 6 mA VIN < 0.3 VCC VIN > 0.7 VCC DA package 30 800 -40 85 500 0.6 DA package DN package 10 10 25 SCL, SDA, A0-A2 SCL, SDA, A0-A2 5 100 400 50 10 2.1 0.8 V V pF kHz kHz ms V A V k k C
1. Guaranteed operating temperature for DA package: TA = -40C to 85C and for DN package: TA = -40C to 125C; VDD = 2.7 V to 3.6 V (except where noted). 2. Typical numbers taken at VDD = 3.3 V, TA = 25C. 3. DN is TDFN package max 0.80 mm height. DA is DFN package max 0.90 mm height.
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Package mechanical data
STTS424E02
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a halogen-free and lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
Figure 15. DFN8 - 8-lead dual flat, no-lead (2 mm x 3 mm) package outline (DA)
DA_ME
1. Drawing is not to scale.
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STTS424E02 Table 28.
Sym Min A A1 A3 b D D2 E E2 e L ddd 0.20 0.20 1.95 1.35 2.95 1.25 0.80 0.00 Typ 0.85 0.00 0.20 0.25 2.00 1.40 3.00 1.30 0.50 0.30 0.40 0.08 0.008 0.30 2.05 1.45 3.05 1.35 0.008 0.075 0.053 0.116 0.049 Max 0.90 0.05 Min 0.031 0.000
Package mechanical data DFN8 - 8-lead dual flat, no-lead (2 mm x 3 mm) mechanical data (DA)
mm inches Typ 0.033 0.000 0.005 0.010 0.078 0.055 0.118 0.051 0.020 0.012 0.016 0.003 0.012 0.079 0.057 0.120 0.053 Max 0.035 0.002
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Package mechanical data
STTS424E02
Figure 16. TDFN8 - 8-lead thin dual flat, no-lead (2 mm x 3 mm) package outline (DN)(a)
DA_ME
a. JEDEC MO-229, variation WCED-3 proposal
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STTS424E02 Table 29.
Sym Min A A1 A3 b D D2 E E2 e L ddd
1. JEDEC MO-229, variation WCED-3 proposal
Package mechanical data TDFN8 - 8-lead thin dual flat, no-lead (2 mm x 3 mm) mechanical data (DN)(1)
mm Typ 0.75 0.00 0.20 0.20 1.95 1.35 2.95 1.25 0.25 2.00 1.40 3.00 1.30 0.50 0.30 0.35 0.40 0.08 0.012 0.30 2.05 1.45 3.05 1.35 0.008 0.075 0.053 0.116 0.049 Max 0.80 0.05 Min 0.028 0.000 inches Typ 0.030 0.000 0.005 0.010 0.078 0.055 0.118 0.051 0.020 0.014 0.016 0.003 0.012 0.079 0.057 0.120 0.053 Max 0.031 0.002
0.70 0.00
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Part numbering
STTS424E02
11
Part numbering
Table 30.
Example:
Ordering information scheme
STTS424E02 B DN 3 F
Device type STTS424E02
Grade B: Maximum accuracy 75C to 95C = 1C C: Maximum accuracy 75C to 95C = 2C
Package DN = TDFN8 (0.80 mm max height)(1) DA = DFN8 (0.90 mm max height)(2)
Temperature 3 = -40C to 125C (DN package only) 6 = -40C to 85C (DA package only)
Shipping method F = ECOPACK(R) package, tape & reel packing E = ECOPACK(R) package, tube packing
1. DN package is only available in B accuracy grade and in temperature grade 3. 2. DA package available only in temperature grade 6.
For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you.
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STTS424E02
Package marking information
12
Package marking information
Figure 17. DA package topside marking information (DFN-8L)
E42X (1) PYWW (2)
ai13907
1. Option codes: X = B or C accuracy grade. For example, E42C is C-grade. 2. Traceability codes P = Plant code Y = Year WW = Work Week
Figure 18. DN package topside marking information (TDFN-8L)
E42X (1) DN (2) PYWW (3)
ai13907b
1. Option codes: X = B or C accuracy grade. For example, E42C is C-grade. 2. TDFN package identifier DN = 0.80 mm (package height) 3. Traceability codes P = Plant code Y = Year WW = Work Week
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Landing pattern
STTS424E02
13
Landing pattern
The landing pattern recommendations per the JEDEC proposal for the TDFN package (DN) are shown in Figure 19. The preferred implementation with wide corner pads enhances device centering during assembly, but a narrower option is defined for modules with tight routing requirements. Figure 19. Landing pattern - TDFN package (DN)
e4 e2 e/2 e e/2
L
K
D2 E3 D2/2 D2/2 E2/2
E2
E2/2 E3
K
L
b2 K2 b4
b K2
b K2
ai14000
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STTS424E02
Landing pattern
Table 31 lists variations of landing pattern implementations, ranked as "Preferred" and Minimum Acceptable" based on the JEDEC proposal. Table 31.
Parameter D2 E2 E3 L K K2 e b e2 b2 e4 b4 Heat paddle width Heat paddle height Heat paddle centerline to contact inner locus Contact length Heat paddle to contact keepout Contact to contact keepout Contact centerline to contact centerline pitch for inner contacts Contact width for inner contacts Landing pattern centerline to outer contact centerline, "minimum acceptable" option(1) Corner contact width, "minimum acceptable option"(1) Landing pattern centerline to outer contact centerline, "preferred" option(2) Corner contact width, "preferred" option(2)
Parameters for landing pattern - TDFN package (DN)
Dimension Description Min 1.40 1.40 1.00 0.70 0.20 0.20 0.25 0.25 0.45 Nom 0.50 0.50 0.60 Max 1.60 1.60 0.80 0.30 0.30 0.50
1. Minimum acceptable option to be used when routing prevents preferred width contact. 2. Preferred option to be used when possible.
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Revision history
STTS424E02
14
Revision history
Table 32.
Date 13-Apr-2007 09-May-2007 04-Jun-2007 02-Jul-2007 18-Mar-2008
Document revision history
Revision 1 2 3 4 5 Initial release. Updated Table 3, 5, 6, 7, 27, 28 and 30. Updated Table 27. Added POR threshold values to Table 27, updated Table 28. Added TDFN package (cover page, Figure 16, Table 29) and landing pattern recommendations (Figure 19, Table 31); updated Section 1, 2, Table 2, 3, 5, 6, 7, 11, 19, 25, 27, 28, 29, 30, Figure 2, 15, 17, 18). Updated cover page, Figure 4, 5, 8, 14; Section 4.3.1,Section 5.4.1; Table 5, 11, 25, 27, 30; added Figure 6; removed TSSOP8 package throughout datasheet. Changes
12-Jun-2008
6
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STTS424E02
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